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<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">PnR Messages</a></li>
<!--<li><a href="#Summary" style=" font-size: 16px;">PnR Summaries</a></li>-->
<li><a href="#PnR_Details" style=" font-size: 16px;">PnR Details</a>
<li><a href="#Resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#Resource_Usage_Summary" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#I/O_Bank_Usage_Summary" style=" font-size: 14px;">I/O Bank Usage Summary</a></li>
<li><a href="#Global_Clock_Usage_Summary" style=" font-size: 14px;">Global Clock Usage Summary</a></li>
<li><a href="#Global_Clock_Signals" style=" font-size: 14px;">Global Clock Signals</a></li>
<li><a href="#Pinout_by_Port_Name" style=" font-size: 14px;">Pinout by Port Name</a></li>
<li><a href="#All_Package_Pins" style=" font-size: 14px;">All Package Pins</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
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<div id="content">
<h1><a name="Message">PnR Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>PnR Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\impl\gwsynthesis\top.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\src\top.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\src\lcd.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.07</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Nov 20 04:37:02 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="PnR_Details">PnR Details</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<table class="summary_table">
<tr>
<td class="label">Place & Route Process</td>
<td>Running placement:
   Placement Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
   Placement Phase 1: CPU time = 0h 0m 0.663s, Elapsed time = 0h 0m 0.663s
   Placement Phase 2: CPU time = 0h 0m 16s, Elapsed time = 0h 0m 16s
   Placement Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s
   Total Placement: CPU time = 0h 0m 36s, Elapsed time = 0h 0m 36s
Running routing:
   Routing Phase 0: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.006s
   Routing Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
   Routing Phase 2: CPU time = 0h 1m 55s, Elapsed time = 0h 1m 55s
   Total Routing: CPU time = 0h 1m 57s, Elapsed time = 0h 1m 57s
Generate output files:
   CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
</td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 2m 37s, Elapsed time = 0h 2m 37s, Peak memory usage = 547MB</td>
</tr>
</table>
<br/>
<h1><a name="Resource">Resource</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>12900/20736</td>
<td>62%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
<td>12042(10719 LUT, 1323 ALU, 0 ROM16)</td>
<td>-</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --SSRAM(RAM16)</td>
<td>143</td>
<td>-</td>
</tr>
<tr>
<td class="label">Register</td>
<td>6725/16173</td>
<td>41%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as Latch</td>
<td>0/15552</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as FF</td>
<td>6718/15552</td>
<td>43%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as Latch</td>
<td>0/621</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as FF</td>
<td>7/621</td>
<td>1%</td>
</tr>
<tr>
<td class="label">CLS</td>
<td>8758/10368</td>
<td>84%</td>
</tr>
<tr>
<td class="label">I/O Port</td>
<td>89</td>
<td>-</td>
</tr>
<tr>
<td class="label">I/O Buf</td>
<td>79</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Input Buf</td>
<td>18</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Output Buf</td>
<td>41</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Inout Buf</td>
<td>20</td>
<td>-</td>
</tr>
<tr>
<td class="label">IOLOGIC</td>
<td>16 IDES8_MEM<br/>24 OSER8<br/>20 OSER8_MEM<br/>4 OSER10<br/>40 IODELAY<br/></td>
<td>61%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>9 SDPB<br/>23 SDPX9B<br/></td>
<td>69%</td>
</tr>
<tr>
<td class="label">DSP</td>
<td>13 MULT9X9<br/>4 MULT18X18<br/>1 MULT36X36<br/>1 MULTALU36X18<br/>7 MULTADDALU18X18<br/></td><td>63%</td>
</tr>
<tr>
<td class="label">PLL</td>
<td>3/4</td>
<td>75%</td>
</tr>
<tr>
<td class="label">DCS</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">DQCE</td>
<td>0/24</td>
<td>0%</td>
</tr>
<tr>
<td class="label">OSC</td>
<td>0/1</td>
<td>0%</td>
</tr>
<tr>
<td class="label">CLKDIV</td>
<td>2/8</td>
<td>25%</td>
</tr>
<tr>
<td class="label">DLLDLY</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">DQS</td>
<td>2/9</td>
<td>22%</td>
</tr>
<tr>
<td class="label">DHCEN</td>
<td>1/16</td>
<td>6%</td>
</tr>
</table>
<h2><a name="I/O_Bank_Usage_Summary">I/O Bank Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>I/O Bank</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label">bank 0</td>
<td>15/29(51%)</td>
</tr>
<tr>
<td class="label">bank 1</td>
<td>7/20(35%)</td>
</tr>
<tr>
<td class="label">bank 2</td>
<td>6/20(30%)</td>
</tr>
<tr>
<td class="label">bank 3</td>
<td>8/32(25%)</td>
</tr>
<tr>
<td class="label">bank 4</td>
<td>21/36(58%)</td>
</tr>
<tr>
<td class="label">bank 5</td>
<td>20/36(55%)</td>
</tr>
<tr>
<td class="label">bank 6</td>
<td>11/18(61%)</td>
</tr>
<tr>
<td class="label">bank 7</td>
<td>0/16(0%)</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Usage_Summary">Global Clock Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Global Clock</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label">PRIMARY</td>
<td>8/8(100%)</td>
</tr>
<tr>
<td class="label">SECONDARY</td>
<td>8/8(100%)</td>
</tr>
<tr>
<td class="label">GCLK_PIN</td>
<td>5/8(62%)</td>
</tr>
<tr>
<td class="label">PLL</td>
<td>3/4(75%)</td>
</tr>
<tr>
<td class="label">CLKDIV</td>
<td>2/8(25%)</td>
</tr>
<tr>
<td class="label">DLLDLY</td>
<td>0/8(0%)</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Signals">Global Clock Signals:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Signal</b></td>
<td><b>Global Clock</b></td>
<td><b>Location</b></td>
</tr>
<tr>
<td class="label">cmos_pclk_d</td>
<td>PRIMARY</td>
<td> TL BL</td>
</tr>
<tr>
<td class="label">video_clk</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">cmos_xclk_d</td>
<td>PRIMARY</td>
<td> TL</td>
</tr>
<tr>
<td class="label">cmos_16bit_clk</td>
<td>PRIMARY</td>
<td> TL BL</td>
</tr>
<tr>
<td class="label">dma_clk</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">serial_clk</td>
<td>PRIMARY</td>
<td> TL</td>
</tr>
<tr>
<td class="label">max_finish</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">clk_50hz_6</td>
<td>PRIMARY</td>
<td> BR</td>
</tr>
<tr>
<td class="label">hdmi4_rst_n</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">mic_clk_d</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">reset_r[1]</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">reset_r[1]</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">ddr_rst</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">clk_cnt_0[1]</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">clk_cnt_0[1]</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">clk_50hz_6</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">memory_clk</td>
<td>HCLK</td>
<td>BOTTOM[0] LEFT[0]</td>
</tr>
<tr>
<td class="label">serial_clk</td>
<td>HCLK</td>
<td>TOP[0]</td>
</tr>
</table>
<br/>
<h2><a name="Pinout_by_Port_Name">Pinout by Port Name:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Port Name</b></td>
<td><b>Diff Pair</b></td>
<td><b>Loc./Bank</b></td>
<td><b>Constraint</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>BankVccio</b></td>
</tr>
<tr>
<td class="label">clk</td>
<td></td>
<td>H11/0</td>
<td>Y</td>
<td>in</td>
<td>IOT27[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">rst_n</td>
<td></td>
<td>C7/6</td>
<td>Y</td>
<td>in</td>
<td>IOL40[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">cmos_vsync</td>
<td></td>
<td>G15/0</td>
<td>Y</td>
<td>in</td>
<td>IOT13[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_href</td>
<td></td>
<td>G14/0</td>
<td>Y</td>
<td>in</td>
<td>IOT13[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_pclk</td>
<td></td>
<td>F13/0</td>
<td>Y</td>
<td>in</td>
<td>IOT8[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_db[0]</td>
<td></td>
<td>T12/2</td>
<td>Y</td>
<td>in</td>
<td>IOR17[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">cmos_db[1]</td>
<td></td>
<td>T11/2</td>
<td>Y</td>
<td>in</td>
<td>IOR24[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">cmos_db[2]</td>
<td></td>
<td>P11/2</td>
<td>Y</td>
<td>in</td>
<td>IOR24[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">cmos_db[3]</td>
<td></td>
<td>R11/2</td>
<td>Y</td>
<td>in</td>
<td>IOR17[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">cmos_db[4]</td>
<td></td>
<td>M15/1</td>
<td>Y</td>
<td>in</td>
<td>IOT40[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_db[5]</td>
<td></td>
<td>M14/1</td>
<td>Y</td>
<td>in</td>
<td>IOT40[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_db[6]</td>
<td></td>
<td>J16/0</td>
<td>Y</td>
<td>in</td>
<td>IOT22[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_db[7]</td>
<td></td>
<td>J14/0</td>
<td>Y</td>
<td>in</td>
<td>IOT22[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">mic_so1</td>
<td></td>
<td>P8/3</td>
<td>Y</td>
<td>in</td>
<td>IOR42[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">mic_so2</td>
<td></td>
<td>T8/3</td>
<td>Y</td>
<td>in</td>
<td>IOR42[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">mic_so3</td>
<td></td>
<td>R8/3</td>
<td>Y</td>
<td>in</td>
<td>IOR29[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">wbuart_rx</td>
<td></td>
<td>T13/2</td>
<td>Y</td>
<td>in</td>
<td>IOR8[B]</td>
<td>LVCMOS25</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">btn[0]</td>
<td></td>
<td>D7/6</td>
<td>Y</td>
<td>in</td>
<td>IOL53[B]</td>
<td>LVCMOS15</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">btn[1]</td>
<td></td>
<td>T2/4</td>
<td>Y</td>
<td>in</td>
<td>IOB48[B]</td>
<td>LVCMOS15</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">btn[2]</td>
<td></td>
<td>T3/4</td>
<td>Y</td>
<td>in</td>
<td>IOB52[B]</td>
<td>LVCMOS15</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">cmos_xclk</td>
<td></td>
<td>G12/0</td>
<td>Y</td>
<td>out</td>
<td>IOT8[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_rst_n</td>
<td></td>
<td>L13/1</td>
<td>Y</td>
<td>out</td>
<td>IOT38[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_pwdn</td>
<td></td>
<td>C10/3</td>
<td>Y</td>
<td>out</td>
<td>IOR39[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">ddr_addr[0]</td>
<td></td>
<td>F7/6</td>
<td>Y</td>
<td>out</td>
<td>IOL45[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[1]</td>
<td></td>
<td>A4/5</td>
<td>Y</td>
<td>out</td>
<td>IOB2[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[2]</td>
<td></td>
<td>D6/5</td>
<td>Y</td>
<td>out</td>
<td>IOB3[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[3]</td>
<td></td>
<td>F8/6</td>
<td>Y</td>
<td>out</td>
<td>IOL35[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[4]</td>
<td></td>
<td>C4/6</td>
<td>Y</td>
<td>out</td>
<td>IOL47[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[5]</td>
<td></td>
<td>E6/6</td>
<td>Y</td>
<td>out</td>
<td>IOL53[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[6]</td>
<td></td>
<td>B1/5</td>
<td>Y</td>
<td>out</td>
<td>IOB8[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[7]</td>
<td></td>
<td>D8/6</td>
<td>Y</td>
<td>out</td>
<td>IOL38[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[8]</td>
<td></td>
<td>A5/5</td>
<td>Y</td>
<td>out</td>
<td>IOB7[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[9]</td>
<td></td>
<td>F9/6</td>
<td>Y</td>
<td>out</td>
<td>IOL31[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[10]</td>
<td></td>
<td>K3/4</td>
<td>Y</td>
<td>out</td>
<td>IOB36[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[11]</td>
<td></td>
<td>B7/6</td>
<td>Y</td>
<td>out</td>
<td>IOL40[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[12]</td>
<td></td>
<td>A3/5</td>
<td>Y</td>
<td>out</td>
<td>IOB4[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_addr[13]</td>
<td></td>
<td>C8/6</td>
<td>Y</td>
<td>out</td>
<td>IOL29[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_bank[0]</td>
<td></td>
<td>H4/5</td>
<td>Y</td>
<td>out</td>
<td>IOB26[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_bank[1]</td>
<td></td>
<td>D3/5</td>
<td>Y</td>
<td>out</td>
<td>IOB9[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_bank[2]</td>
<td></td>
<td>H5/4</td>
<td>Y</td>
<td>out</td>
<td>IOB35[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_cs</td>
<td></td>
<td>P5/4</td>
<td>Y</td>
<td>out</td>
<td>IOB50[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_ras</td>
<td></td>
<td>R4/4</td>
<td>Y</td>
<td>out</td>
<td>IOB52[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_cas</td>
<td></td>
<td>R6/4</td>
<td>Y</td>
<td>out</td>
<td>IOB54[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_we</td>
<td></td>
<td>L2/4</td>
<td>Y</td>
<td>out</td>
<td>IOB30[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_ck</td>
<td>ddr_ck_n</td>
<td>J1,J3/5</td>
<td>Y</td>
<td>out</td>
<td>IOB27</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_cke</td>
<td></td>
<td>J2/4</td>
<td>Y</td>
<td>out</td>
<td>IOB34[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_odt</td>
<td></td>
<td>R3/4</td>
<td>Y</td>
<td>out</td>
<td>IOB48[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_reset_n</td>
<td></td>
<td>B9/6</td>
<td>Y</td>
<td>out</td>
<td>IOL33[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dm[0]</td>
<td></td>
<td>G1/5</td>
<td>Y</td>
<td>out</td>
<td>IOB24[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dm[1]</td>
<td></td>
<td>K5/4</td>
<td>Y</td>
<td>out</td>
<td>IOB40[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_tmds_clk_p</td>
<td>O_tmds_clk_n</td>
<td>G16,H15/0</td>
<td>Y</td>
<td>out</td>
<td>IOT16</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">O_tmds_data_p[0]</td>
<td>O_tmds_data_n[0]</td>
<td>H14,H16/0</td>
<td>Y</td>
<td>out</td>
<td>IOT20</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">O_tmds_data_p[1]</td>
<td>O_tmds_data_n[1]</td>
<td>J15,K16/0</td>
<td>Y</td>
<td>out</td>
<td>IOT24</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">O_tmds_data_p[2]</td>
<td>O_tmds_data_n[2]</td>
<td>K14,K15/1</td>
<td>Y</td>
<td>out</td>
<td>IOT30</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">mic_clk</td>
<td></td>
<td>T6/3</td>
<td>Y</td>
<td>out</td>
<td>IOR53[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">mic_ws</td>
<td></td>
<td>P6/3</td>
<td>Y</td>
<td>out</td>
<td>IOR53[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">led[0]</td>
<td></td>
<td>N16/1</td>
<td>Y</td>
<td>out</td>
<td>IOT52[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">led[1]</td>
<td></td>
<td>L14/1</td>
<td>Y</td>
<td>out</td>
<td>IOT34[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">wbuart_tx</td>
<td></td>
<td>M11/2</td>
<td>Y</td>
<td>out</td>
<td>IOR27[B]</td>
<td>LVCMOS25</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">steer_x</td>
<td></td>
<td>L9/3</td>
<td>Y</td>
<td>out</td>
<td>IOR40[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">steer_y</td>
<td></td>
<td>N8/3</td>
<td>Y</td>
<td>out</td>
<td>IOR40[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_scl</td>
<td></td>
<td>F14/0</td>
<td>Y</td>
<td>io</td>
<td>IOT9[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos_sda</td>
<td></td>
<td>F16/0</td>
<td>Y</td>
<td>io</td>
<td>IOT9[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">ddr_dq[0]</td>
<td></td>
<td>G5/5</td>
<td>Y</td>
<td>io</td>
<td>IOB20[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[1]</td>
<td></td>
<td>F5/5</td>
<td>Y</td>
<td>io</td>
<td>IOB22[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[2]</td>
<td></td>
<td>F4/5</td>
<td>Y</td>
<td>io</td>
<td>IOB18[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[3]</td>
<td></td>
<td>F3/5</td>
<td>Y</td>
<td>io</td>
<td>IOB19[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[4]</td>
<td></td>
<td>E2/5</td>
<td>Y</td>
<td>io</td>
<td>IOB12[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[5]</td>
<td></td>
<td>C1/5</td>
<td>Y</td>
<td>io</td>
<td>IOB14[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[6]</td>
<td></td>
<td>E1/5</td>
<td>Y</td>
<td>io</td>
<td>IOB16[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[7]</td>
<td></td>
<td>B3/5</td>
<td>Y</td>
<td>io</td>
<td>IOB13[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[8]</td>
<td></td>
<td>M3/4</td>
<td>Y</td>
<td>io</td>
<td>IOB42[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[9]</td>
<td></td>
<td>K4/4</td>
<td>Y</td>
<td>io</td>
<td>IOB39[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[10]</td>
<td></td>
<td>N2/4</td>
<td>Y</td>
<td>io</td>
<td>IOB41[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[11]</td>
<td></td>
<td>L1/4</td>
<td>Y</td>
<td>io</td>
<td>IOB38[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[12]</td>
<td></td>
<td>P4/4</td>
<td>Y</td>
<td>io</td>
<td>IOB45[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[13]</td>
<td></td>
<td>H3/4</td>
<td>Y</td>
<td>io</td>
<td>IOB32[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[14]</td>
<td></td>
<td>R1/4</td>
<td>Y</td>
<td>io</td>
<td>IOB44[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dq[15]</td>
<td></td>
<td>M2/4</td>
<td>Y</td>
<td>io</td>
<td>IOB43[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dqs[0]</td>
<td>ddr_dqs_n[0]</td>
<td>G2,G3/5</td>
<td>Y</td>
<td>io</td>
<td>IOB21</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">ddr_dqs[1]</td>
<td>ddr_dqs_n[1]</td>
<td>J5,K6/4</td>
<td>Y</td>
<td>io</td>
<td>IOB37</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
</table>
<br/>
<h2><a name="All_Package_Pins">All Package Pins:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Loc./Bank</b></td>
<td><b>Signal</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>Bank Vccio</b></td>
</tr>
<tr>
<td class="label">L15/0</td>
<td>-</td>
<td>in</td>
<td>IOT2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">D16/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">E14/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">C16/0</td>
<td>-</td>
<td>in</td>
<td>IOT5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">D15/0</td>
<td>-</td>
<td>in</td>
<td>IOT5[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">E16/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">F15/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">F13/0</td>
<td>cmos_pclk</td>
<td>in</td>
<td>IOT8[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">G12/0</td>
<td>cmos_xclk</td>
<td>out</td>
<td>IOT8[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">F14/0</td>
<td>cmos_scl</td>
<td>io</td>
<td>IOT9[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">F16/0</td>
<td>cmos_sda</td>
<td>io</td>
<td>IOT9[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">F12/0</td>
<td>-</td>
<td>in</td>
<td>IOT12[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">G13/0</td>
<td>-</td>
<td>in</td>
<td>IOT12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">G15/0</td>
<td>cmos_vsync</td>
<td>in</td>
<td>IOT13[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">G14/0</td>
<td>cmos_href</td>
<td>in</td>
<td>IOT13[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">G11/0</td>
<td>-</td>
<td>in</td>
<td>IOT14[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">H12/0</td>
<td>-</td>
<td>in</td>
<td>IOT14[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">G16/0</td>
<td>O_tmds_clk_p</td>
<td>out</td>
<td>IOT16[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">H15/0</td>
<td>O_tmds_clk_n</td>
<td>out</td>
<td>IOT16[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">H13/0</td>
<td>-</td>
<td>in</td>
<td>IOT18[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">J12/0</td>
<td>-</td>
<td>in</td>
<td>IOT18[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">H14/0</td>
<td>O_tmds_data_p[0]</td>
<td>out</td>
<td>IOT20[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">H16/0</td>
<td>O_tmds_data_n[0]</td>
<td>out</td>
<td>IOT20[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">J16/0</td>
<td>cmos_db[6]</td>
<td>in</td>
<td>IOT22[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">J14/0</td>
<td>cmos_db[7]</td>
<td>in</td>
<td>IOT22[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">J15/0</td>
<td>O_tmds_data_p[1]</td>
<td>out</td>
<td>IOT24[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">K16/0</td>
<td>O_tmds_data_n[1]</td>
<td>out</td>
<td>IOT24[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">H11/0</td>
<td>clk</td>
<td>in</td>
<td>IOT27[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">J13/0</td>
<td>-</td>
<td>in</td>
<td>IOT27[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">K14/1</td>
<td>O_tmds_data_p[2]</td>
<td>out</td>
<td>IOT30[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">K15/1</td>
<td>O_tmds_data_n[2]</td>
<td>out</td>
<td>IOT30[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">J11/1</td>
<td>-</td>
<td>in</td>
<td>IOT32[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">L12/1</td>
<td>-</td>
<td>in</td>
<td>IOT32[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">L16/1</td>
<td>-</td>
<td>in</td>
<td>IOT34[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">L14/1</td>
<td>led[1]</td>
<td>out</td>
<td>IOT34[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">K13/1</td>
<td>-</td>
<td>in</td>
<td>IOT36[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">K12/1</td>
<td>-</td>
<td>in</td>
<td>IOT36[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">K11/1</td>
<td>-</td>
<td>in</td>
<td>IOT38[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">L13/1</td>
<td>cmos_rst_n</td>
<td>out</td>
<td>IOT38[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">M14/1</td>
<td>cmos_db[5]</td>
<td>in</td>
<td>IOT40[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">M15/1</td>
<td>cmos_db[4]</td>
<td>in</td>
<td>IOT40[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">D14/1</td>
<td>-</td>
<td>in</td>
<td>IOT44[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">E15/1</td>
<td>-</td>
<td>in</td>
<td>IOT44[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">N15/1</td>
<td>-</td>
<td>in</td>
<td>IOT48[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">P16/1</td>
<td>-</td>
<td>in</td>
<td>IOT48[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">N16/1</td>
<td>led[0]</td>
<td>out</td>
<td>IOT52[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">N14/1</td>
<td>-</td>
<td>in</td>
<td>IOT52[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">P15/1</td>
<td>-</td>
<td>in</td>
<td>IOT54[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">R16/1</td>
<td>-</td>
<td>in</td>
<td>IOT54[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">A4/5</td>
<td>ddr_addr[1]</td>
<td>out</td>
<td>IOB2[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">C5/5</td>
<td>-</td>
<td>in</td>
<td>IOB2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">D6/5</td>
<td>ddr_addr[2]</td>
<td>out</td>
<td>IOB3[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E7/5</td>
<td>-</td>
<td>in</td>
<td>IOB3[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">A3/5</td>
<td>ddr_addr[12]</td>
<td>out</td>
<td>IOB4[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B4/5</td>
<td>-</td>
<td>in</td>
<td>IOB4[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">A5/5</td>
<td>ddr_addr[8]</td>
<td>out</td>
<td>IOB7[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B6/5</td>
<td>-</td>
<td>in</td>
<td>IOB7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B1/5</td>
<td>ddr_addr[6]</td>
<td>out</td>
<td>IOB8[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">C2/5</td>
<td>-</td>
<td>in</td>
<td>IOB8[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">D3/5</td>
<td>ddr_bank[1]</td>
<td>out</td>
<td>IOB9[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">D1/5</td>
<td>-</td>
<td>in</td>
<td>IOB9[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E2/5</td>
<td>ddr_dq[4]</td>
<td>io</td>
<td>IOB12[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E3/5</td>
<td>-</td>
<td>in</td>
<td>IOB12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B3/5</td>
<td>ddr_dq[7]</td>
<td>io</td>
<td>IOB13[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">A2/5</td>
<td>-</td>
<td>in</td>
<td>IOB13[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">C1/5</td>
<td>ddr_dq[5]</td>
<td>io</td>
<td>IOB14[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">D2/5</td>
<td>-</td>
<td>in</td>
<td>IOB14[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E1/5</td>
<td>ddr_dq[6]</td>
<td>io</td>
<td>IOB16[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F2/5</td>
<td>-</td>
<td>in</td>
<td>IOB16[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F4/5</td>
<td>ddr_dq[2]</td>
<td>io</td>
<td>IOB18[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">G6/5</td>
<td>-</td>
<td>in</td>
<td>IOB18[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F3/5</td>
<td>ddr_dq[3]</td>
<td>io</td>
<td>IOB19[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F1/5</td>
<td>-</td>
<td>in</td>
<td>IOB19[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">G5/5</td>
<td>ddr_dq[0]</td>
<td>io</td>
<td>IOB20[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">G4/5</td>
<td>-</td>
<td>in</td>
<td>IOB20[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">G2/5</td>
<td>ddr_dqs[0]</td>
<td>io</td>
<td>IOB21[A]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">G3/5</td>
<td>ddr_dqs_n[0]</td>
<td>io</td>
<td>IOB21[B]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F5/5</td>
<td>ddr_dq[1]</td>
<td>io</td>
<td>IOB22[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">H6/5</td>
<td>-</td>
<td>in</td>
<td>IOB22[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">G1/5</td>
<td>ddr_dm[0]</td>
<td>out</td>
<td>IOB24[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">H2/5</td>
<td>-</td>
<td>in</td>
<td>IOB24[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">H4/5</td>
<td>ddr_bank[0]</td>
<td>out</td>
<td>IOB26[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">J6/5</td>
<td>-</td>
<td>in</td>
<td>IOB26[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">J1/5</td>
<td>ddr_ck</td>
<td>out</td>
<td>IOB27[A]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">J3/5</td>
<td>ddr_ck_n</td>
<td>out</td>
<td>IOB27[B]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">L2/4</td>
<td>ddr_we</td>
<td>out</td>
<td>IOB30[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">M1/4</td>
<td>-</td>
<td>in</td>
<td>IOB30[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">H3/4</td>
<td>ddr_dq[13]</td>
<td>io</td>
<td>IOB32[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">H1/4</td>
<td>-</td>
<td>in</td>
<td>IOB32[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">J2/4</td>
<td>ddr_cke</td>
<td>out</td>
<td>IOB34[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">K1/4</td>
<td>-</td>
<td>in</td>
<td>IOB34[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">H5/4</td>
<td>ddr_bank[2]</td>
<td>out</td>
<td>IOB35[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">J4/4</td>
<td>-</td>
<td>in</td>
<td>IOB35[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">K3/4</td>
<td>ddr_addr[10]</td>
<td>out</td>
<td>IOB36[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">K2/4</td>
<td>-</td>
<td>in</td>
<td>IOB36[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">J5/4</td>
<td>ddr_dqs[1]</td>
<td>io</td>
<td>IOB37[A]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">K6/4</td>
<td>ddr_dqs_n[1]</td>
<td>io</td>
<td>IOB37[B]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">L1/4</td>
<td>ddr_dq[11]</td>
<td>io</td>
<td>IOB38[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">L3/4</td>
<td>-</td>
<td>in</td>
<td>IOB38[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">K4/4</td>
<td>ddr_dq[9]</td>
<td>io</td>
<td>IOB39[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">L5/4</td>
<td>-</td>
<td>in</td>
<td>IOB39[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">K5/4</td>
<td>ddr_dm[1]</td>
<td>out</td>
<td>IOB40[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">L4/4</td>
<td>-</td>
<td>in</td>
<td>IOB40[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">N2/4</td>
<td>ddr_dq[10]</td>
<td>io</td>
<td>IOB41[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">P1/4</td>
<td>-</td>
<td>in</td>
<td>IOB41[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">M3/4</td>
<td>ddr_dq[8]</td>
<td>io</td>
<td>IOB42[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">N1/4</td>
<td>-</td>
<td>in</td>
<td>IOB42[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">M2/4</td>
<td>ddr_dq[15]</td>
<td>io</td>
<td>IOB43[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">N3/4</td>
<td>-</td>
<td>in</td>
<td>IOB43[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">R1/4</td>
<td>ddr_dq[14]</td>
<td>io</td>
<td>IOB44[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">P2/4</td>
<td>-</td>
<td>in</td>
<td>IOB44[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">P4/4</td>
<td>ddr_dq[12]</td>
<td>io</td>
<td>IOB45[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">T4/4</td>
<td>-</td>
<td>in</td>
<td>IOB45[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">R3/4</td>
<td>ddr_odt</td>
<td>out</td>
<td>IOB48[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">T2/4</td>
<td>btn[1]</td>
<td>in</td>
<td>IOB48[B]</td>
<td>LVCMOS15</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">P5/4</td>
<td>ddr_cs</td>
<td>out</td>
<td>IOB50[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">R5/4</td>
<td>-</td>
<td>in</td>
<td>IOB50[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">R4/4</td>
<td>ddr_ras</td>
<td>out</td>
<td>IOB52[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">T3/4</td>
<td>btn[2]</td>
<td>in</td>
<td>IOB52[B]</td>
<td>LVCMOS15</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">R6/4</td>
<td>ddr_cas</td>
<td>out</td>
<td>IOB54[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">T5/4</td>
<td>-</td>
<td>in</td>
<td>IOB54[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B14/7</td>
<td>-</td>
<td>in</td>
<td>IOL2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">A15/7</td>
<td>-</td>
<td>in</td>
<td>IOL2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">C12/7</td>
<td>-</td>
<td>in</td>
<td>IOL7[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">B12/7</td>
<td>-</td>
<td>in</td>
<td>IOL7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">B13/7</td>
<td>-</td>
<td>in</td>
<td>IOL8[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">A14/7</td>
<td>-</td>
<td>in</td>
<td>IOL8[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">F10/7</td>
<td>-</td>
<td>in</td>
<td>IOL11[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">B11/7</td>
<td>-</td>
<td>in</td>
<td>IOL13[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">A12/7</td>
<td>-</td>
<td>in</td>
<td>IOL13[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">A11/7</td>
<td>-</td>
<td>in</td>
<td>IOL15[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">C11/7</td>
<td>-</td>
<td>in</td>
<td>IOL15[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">D10/7</td>
<td>-</td>
<td>in</td>
<td>IOL17[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">E10/7</td>
<td>-</td>
<td>in</td>
<td>IOL17[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">D11/7</td>
<td>-</td>
<td>in</td>
<td>IOL22[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">A9/7</td>
<td>-</td>
<td>in</td>
<td>IOL27[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">C9/7</td>
<td>-</td>
<td>in</td>
<td>IOL27[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<tr>
<td class="label">C8/6</td>
<td>ddr_addr[13]</td>
<td>out</td>
<td>IOL29[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">A8/6</td>
<td>-</td>
<td>in</td>
<td>IOL29[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F9/6</td>
<td>ddr_addr[9]</td>
<td>out</td>
<td>IOL31[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E11/6</td>
<td>-</td>
<td>in</td>
<td>IOL31[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B9/6</td>
<td>ddr_reset_n</td>
<td>out</td>
<td>IOL33[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">A10/6</td>
<td>-</td>
<td>in</td>
<td>IOL33[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F8/6</td>
<td>ddr_addr[3]</td>
<td>out</td>
<td>IOL35[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">D9/6</td>
<td>-</td>
<td>in</td>
<td>IOL35[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">D8/6</td>
<td>ddr_addr[7]</td>
<td>out</td>
<td>IOL38[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E9/6</td>
<td>-</td>
<td>in</td>
<td>IOL38[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B7/6</td>
<td>ddr_addr[11]</td>
<td>out</td>
<td>IOL40[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">C7/6</td>
<td>rst_n</td>
<td>in</td>
<td>IOL40[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">F7/6</td>
<td>ddr_addr[0]</td>
<td>out</td>
<td>IOL45[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E8/6</td>
<td>-</td>
<td>in</td>
<td>IOL45[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">C4/6</td>
<td>ddr_addr[4]</td>
<td>out</td>
<td>IOL47[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">B5/6</td>
<td>-</td>
<td>in</td>
<td>IOL47[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">E6/6</td>
<td>ddr_addr[5]</td>
<td>out</td>
<td>IOL53[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">D7/6</td>
<td>btn[0]</td>
<td>in</td>
<td>IOL53[B]</td>
<td>LVCMOS15</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">T15/2</td>
<td>-</td>
<td>in</td>
<td>IOR7[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">R14/2</td>
<td>-</td>
<td>in</td>
<td>IOR7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">P12/2</td>
<td>-</td>
<td>in</td>
<td>IOR8[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">T13/2</td>
<td>wbuart_rx</td>
<td>in</td>
<td>IOR8[B]</td>
<td>LVCMOS25</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">R12/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">P13/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">R11/2</td>
<td>cmos_db[3]</td>
<td>in</td>
<td>IOR17[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">T12/2</td>
<td>cmos_db[0]</td>
<td>in</td>
<td>IOR17[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">R13/2</td>
<td>-</td>
<td>in</td>
<td>IOR20[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">T14/2</td>
<td>-</td>
<td>in</td>
<td>IOR20[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">M10/2</td>
<td>-</td>
<td>in</td>
<td>IOR22[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">N11/2</td>
<td>-</td>
<td>in</td>
<td>IOR22[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">T11/2</td>
<td>cmos_db[1]</td>
<td>in</td>
<td>IOR24[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">P11/2</td>
<td>cmos_db[2]</td>
<td>in</td>
<td>IOR24[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">C6/2</td>
<td>-</td>
<td>out</td>
<td>IOR25[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">B8/2</td>
<td>-</td>
<td>in</td>
<td>IOR25[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">A7/2</td>
<td>-</td>
<td>in</td>
<td>IOR26[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">A6/2</td>
<td>-</td>
<td>in</td>
<td>IOR26[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">N10/2</td>
<td>-</td>
<td>in</td>
<td>IOR27[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">M11/2</td>
<td>wbuart_tx</td>
<td>out</td>
<td>IOR27[B]</td>
<td>LVCMOS25</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">T7/3</td>
<td>-</td>
<td>in</td>
<td>IOR29[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">R8/3</td>
<td>mic_so3</td>
<td>in</td>
<td>IOR29[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">M16/3</td>
<td>-</td>
<td>in</td>
<td>IOR30[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">B16/3</td>
<td>-</td>
<td>in</td>
<td>IOR30[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">C15/3</td>
<td>-</td>
<td>in</td>
<td>IOR31[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">B10/3</td>
<td>-</td>
<td>in</td>
<td>IOR31[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">A13/3</td>
<td>-</td>
<td>in</td>
<td>IOR32[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">C13/3</td>
<td>-</td>
<td>in</td>
<td>IOR32[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">P10/3</td>
<td>-</td>
<td>in</td>
<td>IOR33[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">R10/3</td>
<td>-</td>
<td>in</td>
<td>IOR33[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">M9/3</td>
<td>-</td>
<td>in</td>
<td>IOR34[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">L10/3</td>
<td>-</td>
<td>in</td>
<td>IOR34[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">R9/3</td>
<td>-</td>
<td>in</td>
<td>IOR35[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">T10/3</td>
<td>-</td>
<td>in</td>
<td>IOR35[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">M8/3</td>
<td>-</td>
<td>in</td>
<td>IOR36[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">N9/3</td>
<td>-</td>
<td>in</td>
<td>IOR36[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">T9/3</td>
<td>-</td>
<td>in</td>
<td>IOR38[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">P9/3</td>
<td>-</td>
<td>in</td>
<td>IOR38[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">C10/3</td>
<td>cmos_pwdn</td>
<td>out</td>
<td>IOR39[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">N8/3</td>
<td>steer_y</td>
<td>out</td>
<td>IOR40[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">L9/3</td>
<td>steer_x</td>
<td>out</td>
<td>IOR40[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">P8/3</td>
<td>mic_so1</td>
<td>in</td>
<td>IOR42[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">T8/3</td>
<td>mic_so2</td>
<td>in</td>
<td>IOR42[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">M6/3</td>
<td>-</td>
<td>in</td>
<td>IOR44[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">L8/3</td>
<td>-</td>
<td>in</td>
<td>IOR44[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">M7/3</td>
<td>-</td>
<td>in</td>
<td>IOR47[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">N7/3</td>
<td>-</td>
<td>in</td>
<td>IOR47[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">R7/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">P7/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">N6/3</td>
<td>-</td>
<td>in</td>
<td>IOR51[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">P6/3</td>
<td>mic_ws</td>
<td>out</td>
<td>IOR53[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">T6/3</td>
<td>mic_clk</td>
<td>out</td>
<td>IOR53[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
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